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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
2M (256K x 8) Static RAM
Features
* Very high speed: 55 ns and 70 ns * Voltage range: -- CY62138CV25: 2.2V-2.7V -- CY62138CV30: 2.7V-3.3V -- CY62138CV33: 3.0V-3.6V -- CY62138CV: 2.7V-3.6V * Pin-compatible with CY62138V * Ultra low active power -- Typical active current: 1.5 mA @ f = 1 MHz -- Typical active current: 5.5 mA @ f = fmax (70-ns speed) Low standby power Easy memory expansion with CE1, CE2, and OE features Automatic power-down when deselected CMOS for optimum speed/power Packages offered in a 36-ball FBGA bits. This device features advanced circuit design to provide ultra-low active current. This is ideal for providing More Battery LifeTM (MoBL(R)) in portable applications. The device also has an automatic power-down feature that significantly reduces power consumption by 80% when addresses are not toggling. The device can be put into standby mode reducing power consumption by more than 99% when deselected (CE1 HIGH or CE2 LOW). Writing to the device is accomplished by taking Chip Enable 1 (CE1) and Write Enable (WE) inputs LOW and Chip Enable 2 (CE2) HIGH. Data on the eight I/O pins (I/O0 through I/O7) is then written into the location specified on the address pins (A0 through A17). Reading from the device is accomplished by taking Chip Enable 1 (CE1) and Output Enable (OE) LOW while forcing Write Enable (WE) and Chip Enable 2 (CE2) HIGH. Under these conditions, the contents of the memory location specified by the address pins will appear on the I/O pins. The eight input/output pins (I/O0 through I/O7) are placed in a high-impedance state when the device is deselected (CE1 HIGH or CE2 LOW), the outputs are disabled (OE HIGH), or during a write operation (CE1 LOW, CE2 HIGH and WE LOW). See the truth table at the back of this data sheet for a complete description of read and write modes.
* * * * *
Functional Description[1]
The CY62138CV25/30/33 and CY62138CV are high-performance CMOS static RAMs organized as 256K words by eight
Logic Block Diagram
Data in Drivers
I/O0 I/O1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11
CE1 CE2 WE OE
ROW DECODER
SENSE AMPS
I/O2 I/O3 I/O4 I/O5
256K x 8 ARRAY
COLUMN DECODER
POWER DOWN
I/O6 I/O7
Note: 1. For best practice recommendations, please refer to the Cypress application note "System Design Guidelines" on http://www.cypress.com.
Cypress Semiconductor Corporation Document #: 38-05200 Rev. *D
*
3901 North First Street
A12 A13 A14 A15 A16 A17
*
San Jose
*
CA 95134 * 408-943-2600 Revised September 20, 2002
CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Pin Configuration
[2, 3]
1 A0 I/O4 I/O5 VSS VCC I/O6 I/O7 A9
2 A1 A2
FBGA (Top View)
3 4 5 A3 A4 A5 A6 A7
6 A8 I/O0 I/O1 VCC VSS A B C D E F G H
CE2 WE DNU
NC OE A10 CE1 A11
A17 A16 A12 A15 A13
I/O2 I/O3 A14
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ................................. -65C to +150C Ambient Temperature with Power Applied .............................................. 55C to +125C Supply Voltage to Ground Potential ... -0.5V VCCMAX + 0.5V DC Voltage Applied to Outputs in High-Z State[4] .....................................0.5V to VCC + 0.3V DC Input Voltage[4].................................-0.5V to VCC + 0.3V Output Current into Outputs (LOW) ............................20 mA
Static Discharge Voltage........................................... > 2001V (per MIL-STD-883, Method 3015) Latch-Up Current ................................................... > 200 mA
Operating Range
Product CY62138CV25 CY62138CV30 CY62138CV33 CY62138CV Ambient Range Temperature TA VCC Industrial -40C to +85C 2.2V to 2.7V 2.7V to 3.3V 3.0V to 3.6V 2.7V to 3.6V
Product Portfolio
Power Dissipation Operating, ICC (mA) VCC Range (V) Product CY62138CV25LL CY62138CV30LL CY62138CV33LL CY62138CVLL Min. 2.2 2.7 3.0 2.7 Typ.[5] 2.5 3.0 3.3 3.3 Max. 2.7 3.3 3.6 3.6 Speed (ns) 55 70 55 70 55 70 70 f = 1 MHz Typ.[5] 1.5 1.5 1.5 1.5 1.5 1.5 1.5 Max. 3 3 3 3 3 3 3 f = fmax Typ.[5] 7 5.5 7 5.5 7 5.5 5.5 Max. 15 12 15 12 15 12 12 5 15 5 15 2 10 Typ.[5] 2 Max. 10 Standby, ISB2 (A)
Notes: 2. NC pins are not connected to the die. 3. C3 (DNU) can be left as NC or VSS to ensure proper application. 4. VIL(min.) = -2.0V for pulse durations less than 20 ns. 5. Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C.
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Electrical Characteristics Over the Operating Range
CY62138CV25-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = 2.7V IOUT = 0 mA CMOS Levels Test Conditions IOH = -0.1 mA IOL = 0.1 mA VCC = 2.2V VCC = 2.2V 1.8 -0.3 -1 -1 7 1.5 2 Min. 2.0 0.4 VCC + 0.3V 0.6 +1 +1 15 3 10 1.8 -0.3 -1 -1 5.5 1.5 2 Typ.[5] Max. CY62138CV25-70 Min. Typ.[5] 2.0 0.4 VCC + 0.3V 0.6 +1 +1 12 3 10 A Max. Unit V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs
ISB1
CE1 > VCC - 0.2V or CE2 < 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, WE) CE1 > VCC - 0.2V or CE2 < 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC = 2.7V
ISB2
CY62138CV30-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = 3.3V IOUT = 0 mA CMOS Levels Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 2.7V VCC = 2.7V 2.2 -0.3 -1 -1 7 1.5 2 Min. 2.4 0.4 VCC + 0.3V 0.8 +1 +1 15 3 10 Typ.[5] Max.
CY62138CV30-70 Min. Typ.[5] 2.4 0.4 2.2 -0.3 -1 -1 5.5 1.5 2 VCC + 0.3V 0.8 +1 +1 12 3 10 A Max. Unit V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz Automatic CE Power-down Current -- CMOS Inputs Automatic CE Power-down Current -- CMOS Inputs
ISB1
CE1 > VCC - 0.2V or CE2 < 0.2V VIN > VCC - 0.2V or VIN < 0.2V, f = fmax (Address and Data Only), f = 0 (OE, WE) CE1 > VCC - 0.2V or CE2 < 0.2V, VIN > VCC - 0.2V or VIN < 0.2V, f = 0, VCC=3.3V
ISB2
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Electrical Characteristics Over the Operating Range
CY62138CV33-55 Parameter VOH VOL VIH VIL IIX IOZ ICC Description Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current GND < VI < VCC Output Leakage Current GND < VO < VCC, Output Disabled VCC = 3.6V IOUT = 0 mA CMOS Levels Test Conditions IOH = -1.0 mA IOL = 2.1 mA VCC = 3.0V VCC = 2.7V VCC = 3.0V VCC = 2.7V 2.2 -0.3 -1 -1 7 1.5 5 VCC + 0.3V 0.8 +1 +1 15 3 15 2.2 -0.3 -1 -1 5.5 1.5 5 0.4 Min. Typ.[5] 2.4 Max. CY62138CV33-70 CY62138CV-70 Min. Typ.[5] 2.4 2.4 0.4 0.4 VCC + 0.3V 0.8 +1 +1 12 3 15 A Max. Unit V V V V V V A A mA
VCC Operating Supply f = fMAX = 1/tRC Current f = 1 MHz
ISB1
Automatic CE CE1 > VCC - 0.2V or CE2 < 0.2V Power-down Current-- VIN > VCC - 0.2V or VIN < 0.2V, CMOS Inputs f = fmax (Address and Data Only), f = 0 (OE,WE) Automatic CE CE1 > VCC - 0.2V or CE2 < 0.2V Power-down Current-- VIN > VCC - 0.2V or VIN < 0.2V, CMOS Inputs f = 0, VCC = 3.6V
ISB2
Capacitance[6]
Parameter CIN COUT Description Input Capacitance Output Capacitance Test Conditions TA = 25C, f = 1 MHz, VCC = VCC(typ.) Max. 6 8 Unit pF pF
Thermal Resistance
Parameter JA JC Description Thermal (Junction to Ambient) Resistance[6] Test Conditions Still Air, soldered on a 3 x 4.5 inch, two-layer printed circuit board BGA 55 16 Unit C/W C/W
Thermal Resistance[6] (Junction to Case)
AC Test Loads and Waveforms
R1 VCC OUTPUT 30 pF INCLUDING JIG AND SCOPE R2 VCC Typ 10% GND
Rise Time: 1 V/ns
ALL INPUT PULSES 90% 90% 10%
Fall time: 1 V/ns
Equivalent to:
THEVENIN EQUIVALENT RTH VTH
OUTPUT
Note: 6. Tested initially and after any design or process changes that may affect these parameters.
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Parameters R1 R2 RTH VTH 2.5V 16600 15400 8000 1.20 3.0V 1105 1550 645 1.75 3.3V 1216 1374 645 1.75 Typ.[5] 1 Unit V
Data Retention Characteristics (Over the Operating Range)
Parameter VDR ICCDR Description VCC for Data Retention Data Retention Current VCC = 1.5V CE1 > VCC - 0.2V or CE2 < 0.2V VIN > VCC - 0.2V or VIN < 0.2V 0 tRC Conditions Min. 1.5 Max. VCC(max.) 6 Unit V A
tCDR[6] tR[7]
Chip Deselect to Data Retention Time Operation Recovery Time
ns ns
Data Retention Waveform
DATA RETENTION MODE VCC CE1 VCC(min.) tCDR VDR > 1.5 V VCC(min.) tR
or
CE2
Switching Characteristics Over the Operating Range[8]
55 ns Parameter Read Cycle tRC tAA tOHA tACE tDOE tLZOE tHZOE tLZCE tHZCE tPU tPD Write tWC tSCE Cycle[11] Write Cycle Time 55 70 ns Read Cycle Time Address to Data Valid Data Hold from Address Change CE1 LOW and CE2 HIGH to Data Valid OE LOW to Data Valid OE LOW to Low-Z[9] Low-Z[9] 5 20 10 20 0 55 0 70 10 25 OE HIGH to High-Z[9, 10] CE1 LOW and CE2 HIGH to CE1 HIGH or CE2 LOW to High-Z[9, 10] CE1 LOW and CE2 HIGH to Power-up CE1 HIGH or CE2 LOW to Power-down 10 55 25 5 25 55 55 10 70 35 70 70 ns ns ns ns ns ns ns ns ns ns ns Description Min. Max. Min. 70 ns Max. Unit
CE1 LOW and CE2 HIGH to Write End 45 60 ns Notes: 7. Full-device AC operation requires linear VCC ramp from VDR to VCC(min.) > 100 s or stable at VCC(min.) > 100 s. 8. Test conditions assume signal transition time of 5 ns or less, timing reference levels of VCC(typ.)/2, input pulse levels of 0 to VCC(typ.), and output loading of the specified IOL/IOH and 30-pF load capacitance. 9. At any given temperature and voltage condition, tHZCE is less than tLZCE, tHZOE is less than tLZOE, and tHZWE is less than tLZWE for any given device. 10. tHZOE, tHZCE, and tHZWE transitions are measured when the outputs enter a high-impedance state. 11. The internal write time of the memory is defined by the overlap of WE, CE1 = VIL, and CE2 = VIH. All signals must be ACTIVE to initiate a write and any of these signals can terminate a write by going INACTIVE. The data input set-up and hold timing should be referenced to the edge of the signal that terminates the write.
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Switching Characteristics Over the Operating Range[8] (continued)
55 ns Parameter tAW tHA tSA tPWE tSD tHD tHZWE tLZWE Description Address Set-up to Write End Address Hold from Write End Address Set-up to Write Start WE Pulse Width Data Set-up to Write End Data Hold from Write End WE LOW to High-Z[9, 10] WE HIGH to Low-Z[9] 10 Min. 45 0 0 40 25 0 20 10 Max. Min. 60 0 0 45 30 0 25 70 ns Max. Unit ns ns ns ns ns ns ns ns
Switching Waveforms
Read Cycle No. 1 (Address Transition Controlled) [12, 13]
tRC ADDRESS tAA tOHA DATA OUT PREVIOUS DATA VALID DATA VALID
Read Cycle No. 2 (OE Controlled) [13, 14]
ADDRESS tRC CE1 CE2 tACE OE tHZOE tDOE tLZOE HIGH IMPEDANCE tLZCE VCC SUPPLY CURRENT tPU 50% tHZCE DATA VALID tPD 50% ISB ICC HIGH IMPEDANCE
DATA OUT
Notes: 12. Device is continuously selected. OE, CE1 = VIL, CE2=VIH. 13. WE is HIGH for read cycle. 14. Address valid prior to or coincident with CE1 transition LOW and CE2 transition HIGH.
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 1 (WE Controlled)
[11, 15, 17]
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tPWE tHA
OE tSD DATA I/O NOTE 16 tHZOE DATAIN VALID tHD
[11, 15, 17]
Write Cycle No. 2 (CE1 or CE2 Controlled)
tWC ADDRESS tSCE CE1 tSA CE2 tAW tPWE WE tHA
OE tSD DATA I/O DATAIN VALID tHD
Notes: 15. Data I/O is high impedance if OE = VIH. 16. During this period, the I/Os are in output state and input signals should not be applied. 17. If CE1 goes HIGH or CE2 goes LOW simultaneously with WE HIGH, the output remains in high-impedance state.
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Switching Waveforms (continued)
Write Cycle No. 3 (WE Controlled, OE LOW)
[17]
tWC ADDRESS tSCE CE1
CE2 tAW tSA WE tSD DATAI/O NOTE 16 tHZWE DATAIN VALID tLZWE tHD tPWE tHA
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Typical DC and AC Parameters
(Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at VCC = VCC(typ.), TA = 25C)
Operating Current vs. Supply Voltage
14.0 12.0 ICC (mA)
14.0 12.0 ICC (mA) ICC (mA) 10.0 MoBL 8.0 6.0 4.0 2.0 (f = fmax, 55 ns) (f = fmax, 70 ns) (f = 1MHz)
14.0 12.0 10.0 MoBL 8.0 6.0 4.0 2.0 (f = 1MHz) 0.0 3.0 2.7 3.3 SUPPLY VOLTAGE (V) (f = fmax, 55 ns) (f = fmax, 70 ns)
14.0 12.0 ICC (mA) 10.0 8.0 6.0 4.0 2.0 MoBL (f = fmax, 55 ns) (f = fmax, 70 ns)
10.0 8.0 6.0 4.0 2.0 MoBL (f = fmax, 55 ns) (f = fmax, 70 ns) (f = 1MHz)
0.0 2.2 2.5 2.7 SUPPLY VOLTAGE (V)
0.0 3.6 3.3 3.0 SUPPLY VOLTAGE (V)
(f = 1MHz) 0.0 3.6 3.3 2.7 SUPPLY VOLTAGE (V)
Standby Current vs. Supply Voltage
12.0 ISB (A) ISB (A) 10.0 8.0 6.0 4.0 2.0 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) MoBL 12.0 10.0 8.0 6.0 4.0 2.0 0 2.7 3.0 3.3 SUPPLY VOLTAGE (V) ISB (A) MoBL 12.0 MoBL 8.0 6.0 4.0 2.0 0 3.0 3.3 3.6 SUPPLY VOLTAGE (V) ISB (A) 10.0 12.0 MoBL 10.0 8.0 6.0 4.0 2.0 0 2.7 3.3 3.6 SUPPLY VOLTAGE (V)
Access Time vs. Supply Voltage
60 50 40 TAA (ns) TAA (ns) 30 20 10 0 2.2 2.5 2.7 SUPPLY VOLTAGE (V) 60 MoBL 50 40 TAA (ns) 30 20 10 0 2.7 3.0 3.3 60 50 40 TAA (ns) 30 20 10 0 3.0 3.3 3.6 60 50 40 30 20 10 0 2.7 3.3 3.6
MoBL
MoBL
MoBL
SUPPLY VOLTAGE (V)
SUPPLY VOLTAGE (V)
Truth Table
CE1 H X L L L CE2 X L H H H WE X X H H L OE X X L H X Inputs/Outputs High-Z High-Z Data Out (I/O0-I/O7) High-Z Data in (I/O0-I/O7) Mode Deselect/Power-down Deselect/Power-down Read Output Disabled Write
SUPPLY VOLTAGE (V)
Power Standby (ISB) Standby (ISB) Active (ICC) Active (Icc) Active (Icc)
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Ordering Information
Speed (ns) 70 Ordering Code CY62138CV25LL-70BAI CY62138CV25LL-70BVI CY62138CV30LL-70BAI CY62138CV30LL-70BVI CY62138CV33LL-70BAI CY62138CV33LL-70BVI CY62138CVLL-70BAI CY62138CVLL-70BVI 55 CY62138CV25LL-55BAI CY62138CV25LL-55BVI CY62138CV30LL-55BAI CY62138CV30LL-55BVI CY62138CV33LL-55BAI CY62138CV33LL-55BVI Voltage Range (V) 2.2-2.7 2.2-2.7 2.7-3.3 2.7-3.3 3.0-3.6 3.0-3.6 2.7-3.6 2.7-3.6 2.2-2.7 2.2-2.7 2.7-3.3 2.7-3.3 3.0-3.6 3.0-3.6 Package Name BA36A BV36A BA36A BV36A BA36A BV36A BA36A BV36A BA36A BV36A BA36A BV36A BA36A BV36A Package Type 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) 36-ball Fine Pitch BGA (7 mm x 7 mm x 1.2 mm) 36-ball Fine Pitch BGA (6 mm x 8 mm x 1 mm) Operating Range Industrial
Package Diagrams
36-ball FBGA (7 x 7 x 1.2 mm) BA36A
51-85099-*C
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CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Package Diagrams (continued)
36-Lead VFBGA (6 x 8 x 1 mm) BV36A
51-85149-*A
MoBL is a registered trademark and More Battery Life is a trademark of Cypress Semiconductor Corporation. All product and company names mentioned in this document may be the trademarks of their respective holders.
Document #: 38-05200 Rev. *D
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(c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges.
CY62138CV25/30/33 MoBL(R) CY62138CV MoBL(R)
Document History Page
Document Title: CY62138CV25/30/33 MoBL(R)/CY62138CV MoBL(R) 2M (256K x 8) Static RAM Document Number: 38-05200 REV. ** *A *B *C ECN NO. 112381 114024 117062 118123 Issue Date 02/19/02 04/25/02 07/12/02 09/09/02 Orig. of Change GAV JUI MGN MGN Description of Change New Data Sheet (advance information) Added BV package diagram Changed from Advance Information to Preliminary Added Second Chip Enable Changed from Preliminary to Final Added new part number: CY62138CV with wider voltage (2.7V - 3.6V) For TAA = 55 ns, improved tPWE min. from 45 ns to 40 ns For TAA = 70 ns, improved tPWE min. from 60 ns to 45 ns For TAA = 70 ns, improved tLZWE min. from 5 ns to 10 ns Improved Typ. ICC spec. to 7 mA (for 55 ns) and 5.5 mA (for 70 ns). Improved Max ICC spec. to 15 mA (for 55 ns) and 12 mA (for 70 ns). For TAA = 55 ns, improved tLZWE min. from 5 ns to 10 ns. Changed upper spec. for Supply Voltage to Ground Potential to VCCMAX + 0.5V. Changed upper spec for DC Voltage Applied to Ouputs in High-Z State and DC Input Voltage to VCC + 0.3V.
*D
118760
09/23/02
MGN
Document #: 38-05200 Rev. *D
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